加法器~ 4/18

module add(Cout,Sum,A,B,Cin);
output Cout,Sum;
input A,B,Cin;

xor I1(xor_ab,A,B);
and I2(and_ab,A,B);

xor I3(Sum,xor_ab,Cin);
and I4(and_abCin,xor_ab,Cin);

or I5(Cout,and_ab,and_abCin);

endmodule

module top;


wire Cout,Sum, A, B;
wire Cin;

system_clock #100 clock1(B);
system_clock #200 clock2(A);

system_clock #400 clock6(Cin);


add I3(Cout,Sum,A,B,Cin);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule