政輝

2013年5月23日星期四

module test_regfile;

reg [4:0] ra1, wa;
reg clk, en_write;
wire [31:0] rd1;
reg [31:0] wd;

regfile_behavorial A1(ra1, rd1, clk, en_write, wa, wd);

initial
begin

en_write = 1;clk = 0;ra1 = 0;wa = 5'b01010;wd = 32'h11110011;

#100

en_write = 1;clk = 1;ra1 = 0;wa = 5'b01010;wd = 32'h11110011;

#100

en_write = 0;clk = 0;ra1 = 5'b01010;wa = 5'b01010;wd = 32'h11110011;

#100

en_write = 0;clk = 1;ra1 = 5'b01010;wa = 5'b01010;wd = 32'h11110011;

#100

$finish;
end
endmodule

module regfile_behavorial(ra1,rd1,clk,en_write,wa,wd);

input [4:0] ra1, wa;
input clk, en_write;
output [31:0] rd1;
input [31:0] wd;

reg [31:0] registers[31:0];
// 暫存器0永遠輸出0
assign rd1 = (ra1 == 5'b00000) ? 32'h00000000 : registers[ra1];

// 當en_write=1時，執行將wd寫入暫存器的動作
always @(posedge clk)
begin
if ( en_write )
registers[wa] <= wd;
end

endmodule

2013年4月25日星期四

二位元加法器˙.3˙

module add2(Cout,Sum,A,B,Cin);
output Cout;
output [1:0]Sum;
input [1:0]A,B;
input Cin;

add hi(Cout,Sum[1],A[1],B[1],Cin);
add lo(Cout,Sum[0],A[0],B[0],Cin);

endmodule

module add(Cout,Sum,A,B,Cin);
output Cout,Sum;
input A,B,Cin;

xor I1(xor_ab,A,B);
and I2(and_ab,A,B);

xor I3(Sum,xor_ab,Cin);
and I4(and_abCin,xor_ab,Cin);

or I5(Cout,and_ab,and_abCin);

endmodule

module top;

wire Cout;
wire [1:0]A, B,Sum;
wire Cin;

system_clock #100 clock1(B[1]);
system_clock #200 clock2(A[0]);

system_clock #100 clock1(B[1]);
system_clock #200 clock2(A[0]);

system_clock #400 clock6(Cin);

add2 I3(Cout,Sum,A,B,Cin);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
begin
#(PERIOD/2) clk=~clk;
end

always@(posedge clk)
if($time>1000)$stop;

endmodule

2013年4月18日星期四

加法器~ 4/18

module add(Cout,Sum,A,B,Cin);
output Cout,Sum;
input A,B,Cin;

xor I1(xor_ab,A,B);
and I2(and_ab,A,B);

xor I3(Sum,xor_ab,Cin);
and I4(and_abCin,xor_ab,Cin);

or I5(Cout,and_ab,and_abCin);

endmodule

module top;

wire Cout,Sum, A, B;
wire Cin;

system_clock #100 clock1(B);
system_clock #200 clock2(A);

system_clock #400 clock6(Cin);

add I3(Cout,Sum,A,B,Cin);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
begin
#(PERIOD/2) clk=~clk;
end

always@(posedge clk)
if($time>1000)$stop;

endmodule