module test_regfile;


 reg [4:0] ra1, wa;
 reg clk, en_write;
 wire [31:0] rd1;
 reg [31:0] wd;

regfile_behavorial A1(ra1, rd1, clk, en_write, wa, wd);

initial
  begin

en_write = 1;clk = 0;ra1 = 0;wa = 5'b01010;wd = 32'h11110011;

#100

en_write = 1;clk = 1;ra1 = 0;wa = 5'b01010;wd = 32'h11110011;

#100

en_write = 0;clk = 0;ra1 = 5'b01010;wa = 5'b01010;wd = 32'h11110011;

#100

en_write = 0;clk = 1;ra1 = 5'b01010;wa = 5'b01010;wd = 32'h11110011;

#100

    $finish;
  end
endmodule


module regfile_behavorial(ra1,rd1,clk,en_write,wa,wd);

input [4:0] ra1, wa;
input clk, en_write;
output [31:0] rd1;
input [31:0] wd;


 reg [31:0] registers[31:0];
 // 暫存器0永遠輸出0
 assign rd1 = (ra1 == 5'b00000) ? 32'h00000000 : registers[ra1];

 // 當en_write=1時，執行將wd寫入暫存器的動作
 always @(posedge clk)
 begin
  if ( en_write )
   registers[wa] <= wd;
 end

endmodule